ESST / Modules / Memory Stress

Memory Stress

Cache, DRAM, and Rowhammer Stress Testing

Overview

The Memory Stress module provides a suite of algorithms designed to thoroughly test and stress various components of your system's memory hierarchy, including L1/L2 caches, main memory (DRAM), and non-temporal writes. These routines aim to expose potential instabilities and measure performance under extreme memory pressure.

Algorithms

L1/L2 Cache Flooding

Intensive L1/L2 cache flooding with multiple access patterns, including sequential, stride, reverse stride, and random-ish accesses, to maximize cache pressure and identify bottlenecks.

; Multi-pattern cache flooding for maximum pressure mov r12, rdi ; current position ; Pattern 1: Sequential write with prefetch mov [r12], rax prefetchnta [r12 + 512] add r12, 64

Intensive Memory Flooding

Intensive main memory (DRAM) flooding utilizing burst writes, read-modify-write operations, and a mix of non-temporal and regular stores to stress memory bandwidth and latency.

; Burst write pattern 1 mov [r12], rax mov [r12 + 8], r10 mov [r12 + 16], r11 ; Read-modify-write pattern mov r13, [r12] xor r13, rax mov [r12], r13

Aggressive Rowhammer Attack

An aggressive Rowhammer implementation targeting multiple memory locations with alternating and rapid-fire patterns, including cache line flushes, to induce bit flips.

; Hammer sequence 1: Alternating pattern mov [rdi], rax mov [r9], r12 clflush [rdi] clflush [r9] mfence

Non-Temporal Flooding

Intensive non-temporal memory flooding using streaming write patterns, including sequential bursts, interleaved regular stores, and reverse direction writes, to bypass caches and directly stress main memory.

; Streaming pattern 1: Sequential burst movnti [r13], rax movnti [r13 + 8], r10 ; Streaming pattern 2: Interleaved with regular stores movnti [r13], rax mov [r13 + 64], r10

Hardware Stress Targets

फास्ट

CPU Caches (L1, L2, L3)

Algorithms are designed to flood and thrash different levels of the CPU cache hierarchy with varied access patterns, testing cache eviction policies and performance.

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Main Memory (DRAM)

Direct and non-temporal memory accesses maximize bandwidth utilization and stress the memory controller and DRAM modules.

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Memory Controller

Aggressive and concurrent memory operations place high demands on the integrated memory controller, testing its stability and throughput.

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Memory Bandwidth & Latency

Continuous read and write operations, including non-temporal stores, aim to saturate available memory bandwidth and expose latency issues.

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Rowhammer Vulnerability

Specific patterns designed to rapidly activate and deactivate DRAM rows, aiming to induce bit flips in adjacent memory cells.

Performance Characteristics

Memory Access Patterns

Sequential Access Type
Random-ish Access Type
Stride Access Type
Non-Temporal Store Type

Technical Implementation

Key Features:

  • Multiple distinct access patterns for comprehensive cache and memory stress.
  • Utilizes `prefetchnta` for cache flooding to influence cache behavior.
  • Employs `movnti` instructions for non-temporal stores to bypass caches and directly write to memory.
  • Includes `clflush` and `mfence` instructions for explicit cache line flushing and memory fence operations, crucial for Rowhammer.
  • Read-modify-write patterns to engage both read and write paths of the memory subsystem.
  • Large strides and burst writes to maximize memory bandwidth utilization.

Assembly Optimizations:

  • Hand-optimized assembly for precise control over memory access patterns.
  • Direct register manipulation for efficient address calculation and data movement.
  • Loop unrolling for sustained memory access rates.
  • Strategic use of `sfence` to ensure non-temporal writes are committed to memory.
⚠️ Performance Impact & System Stability

This module is designed to place extreme stress on your system's memory subsystem. Extended execution, especially of the Rowhammer attack, may lead to system instability, crashes, or data corruption. Ensure adequate cooling and back up critical data before running intensive memory stress tests. Exercise caution and monitor system behavior closely.

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